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cy7c1386d cy7c1387d 18-mbit (512 k 36/1 m 18) pipelined dcd sync sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05545 rev. *j revised july 24, 2012 18-mbit (512 k 36/1 m 18) pipelined dcd sync sram features supports bus operation up to 200 mhz available speed grades are 200, and 167 mhz registered inputs and outputs for pipelined operation optimal for performance (double-cycle deselect) depth expansion wit hout wait state 3.3 v core power supply (v dd ) 2.5 v or 3.3 v i/o power supply (v ddq) fast clock-to-output times ? 3 ns (for 200 mhz device) provides high performance 3-1-1-1 access rate user selectable burst counter supporting intel ? ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed writes asynchronous output enable cy7c1386d available in jedec-standard pb-free 100-pin tqfp. cy7c1387d available in jedec-standard pb-free 100-pin tqfp and non pb-free 165-ball bga package ieee 1149.1 jtag-compatible boundary scan zz sleep mode option functional description the cy7c1386d/cy7c1387d sram integrates 512 k 36/1 m 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive edge triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables ( bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self timed write cycl e.this part supports byte write operations (see pin configurations on page 5 and truth table on page 10 for further details). write cycl es can be one to four bytes wide as controlled by the byte write control inputs. gw active low causes all bytes to be writte n. this device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.this feature allows dep th expansion without penalizing system performance. the cy7c1386d/cy7c1387d operates from a +3.3 v core power supply while all outputs operate with a +3.3 v or +2.5 v supply. all inputs and outputs are jedec-standard and jesd8-5-compatible. selection guide description 200 mhz 167 mhz unit maximum access time 3.0 3.4 ns maximum operating current 300 275 ma maximum cmos standby current 70 70 ma
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 2 of 34 logic block diagram ? cy7c1386d address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bw d bw c bw b bw a bwe gw ce 1 ce 2 ce 3 oe dq d, dqp d byte write register dq c ,dqp c byte write register dq b ,dqp b byte write register dq a, dqp a byte write register enable register pipelined enable output registers sense amps memory array output buffers dq a, dqp a byte write driver dq b ,dqp b byte write driver dq c ,dqp c byte write driver dq d, dqp d byte write driver input registers a0,a1,a a[1:0] control zz e 2 dqs dqp a dqp b dqp c dqp d
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 3 of 34 logic block diagram ? cy7c1387d address register adv clk burst counter and clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b byte write register dq a , dqp byte write register enable register oe sense amps memory array adsp 2 a [1:0] mode ce 2 ce 3 bwe pipelined enable dq s, dqp a dqp b output registers input registers e output buffers dq b , dqp b byte dq a, dqp a byte sleep control a0, a1, a
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 4 of 34 contents pin configurations ........................................................... 5 pin definitions .................................................................. 7 functional overview ........................................................ 8 single read accesses ................................................ 8 single write accesses initia ted by adsp ................... 8 single write accesses initiate d by adsc ................... 9 burst sequences ......................................................... 9 sleep mode ................................................................. 9 interleaved burst address table (mode = floating or vdd) ................................................. 9 linear burst address table (mode = gnd) ............... 9 zz mode electrical characteri stics .............................. 9 truth table ...................................................................... 10 truth table for read/write ............................................ 11 truth table for read/write ............................................ 11 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 12 disabling the jtag feature ...................................... 12 test access port (tap) ............................................. 12 performing a tap r eset .......... .............. .......... 12 tap registers ...................................................... 12 tap instruction set ................................................... 12 tap controller state diagram ....................................... 14 tap controller block diagram ...................................... 15 tap timing diagram ...................................................... 15 tap ac switching characteristics ............................... 16 3.3 v tap ac test conditions ....................................... 17 3.3 v tap ac output load equivalent ......................... 17 2.5 v tap ac test conditions ....................................... 17 2.5 v tap ac output load equivalent ......................... 17 tap dc electrical characteristics and operating conditions ....................................................................... 17 identification register definitions ................................ 18 scan register sizes ....................................................... 18 identification codes ....................................................... 18 boundary scan order .................................................... 19 maximum ratings ........................................................... 20 operating range ............................................................. 20 neutron soft error immunity ......................................... 20 electrical characteristics ............................................... 20 capacitance .................................................................... 21 thermal resistance ........................................................ 21 ac test loads and waveforms ..................................... 22 switching characteristics .............................................. 23 switching waveforms .................................................... 24 ordering information ...................................................... 28 ordering code definitions ..... .................................... 28 package diagrams .......................................................... 29 acronyms ........................................................................ 30 document conventions ................................................. 30 units of measure ....................................................... 30 document history page ................................................. 31 sales, solutions, and legal information ...................... 34 worldwide sales and design s upport ......... .............. 34 products .................................................................... 34 psoc solutions .................................................................34
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 5 of 34 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout (3 chip enable) a a a a a 1 a 0 nc/72m nc/36m v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1386d (512 k 36) nc a a a a a 1 a 0 nc/72m nc/36m v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1387d (1 m 18) nc a a
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 6 of 34 figure 2. 165-ball fbga (13 15 1.4 mm) pinout (3 chip enable) pin configurations (continued) cy7c1387d (1 m 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m nc nc dqp b nc dq b a ce 1 nc ce 3 bw b bwe a ce 2 nc dq b dq b mode nc dq b dq b nc nc nc nc/36m nc/72m v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd ?v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc/576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 7 of 34 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1:a0 are fed to the two-bit counter. bw a , bw b , bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or desele ct the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or dese lect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or deselect the device. no t connected for bga. where referenced, ce 3 is assumed active throughout this document for bga. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high , dq pins are tristated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically incr ements the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz sleep input, active high . when asserted high places the device in a non-time critical sleep condition with data integrity preser ved. for normal operation, this pin has to be low. zz pin has an internal pull down. dqs, dqp x i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, t hey deliver the data contained in t he memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tristate condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ssq i/o ground ground for the i/o circuitry . v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and must remain static during device operation. mode pin has an internal pull up.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 8 of 34 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. the cy7c1386d/cy7c1387d supports secondary cache in systems using either a linear or interleaved burst sequence. the interleaved burst order supports pentium ? and i486 ? processors. the linear burst sequence is suited for processors that use a linear burst sequenc e. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for t he rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self timed write circuitry. synchronous chip selects ce 1 , ce 2 , ce 3 and an asynchronous output enable (oe ) provide for easy bank selection and output tristate control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) chip selects are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within t co if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always tristated during the fi rst cycle of the access. after the first cycle of the access, the ou tputs are contro lled by the oe signal. consecutive single read cycles are supported. the cy7c1386d/cy7c1387d is a double cycle deselect part. after the sram is deselected at cl ock rise by the chip select and either adsp or adsc signals, its output tristates immediately after the next clock rise. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low and (2) chip select is asserted active. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dq x inputs is written into the corresponding address location in the memory core. if gw is high, the write operation is controlled by bwe and bw x signals. the cy7c1386d/cy7c1387d provides byte write capability that is described in the write cycle description table. asserting the byte write enable input (bwe ) with the selected byte write input, selectively writes to the desired bytes. bytes not selected during a byte write operation remains unaltered. a synchronous self tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not used, this pin must be disconnected. th is pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tc k. if the jtag feature is not used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tc k. if the jtag feature is not used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to th e jtag circuitry . if the jtag feature is not used, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die. nc/(36 m, 72 m, 144 m, 288 m, 576 m, 1 g) ? these pins are not connected. they are used for expansion up to 36 m, 72 m, 144 m, 288 m, 576 m, and 1g densities. pin definitions (continued) name i/o description
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 9 of 34 timed write mechanism has been provided to simplify the write operations. the cy7c1386d/cy7c1387d is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. this tristates the output drivers. as a safety precaution, dq are autom atically tristated whenever a write cycle is detected, regar dless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired byte(s). adsc triggered write accesses require a single clock cycle to complete. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dq x is written into the corresponding address location in the memory core. if a byte write is conduc ted, only the selected bytes are written. bytes not selected duri ng a byte write operation remains unaltered. a synchronous self timed write mechanism has been provided to simplify the write operations. the cy7c1386d/cy7c1387d is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq x inputs. this tristates the output drivers. as a safety precaution, dq x are automatically tristated whenever a write cycle is detected, regar dless of the state of oe . burst sequences the cy7c1386d/cy7c1387d provides a two-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the in terleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. asserting adv low at clock rise auto matically increments the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conserva tion sleep mode. two clock cycles are required to enter into or exit from this sleep mode. while in this mode, data integrity is guaranteed. accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the sleep mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 80 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current this parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curre nt this parameter is sampled 0 ? ns
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 10 of 34 truth table the truth table for cy7c1386d and cy7c1387d follow. [1, 2, 3, 4, 5] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power-down none h x x l x l x x x l?h tristate deselect cycle, power-down none l l x l l x x x x l?h tristate deselect cycle, power-down none l x h l l x x x x l?h tristate deselect cycle, power-down none l l x l h l x x x l?h tristate deselect cycle, power-down none l x h l h l x x x l?h tristate sleep mode, power-down none x x x h x x x x x x tristate read cycle, begin burst external l h l l l x x x l l?h q read cycle, begin burst external l h l l l x x x h l?h tristate write cycle, begin burst external l h l l h l x l x l?h d read cycle, begin burst external l h l l h l x h l l?h q read cycle, begin burst external l h l l h l x h h l?h tristate read cycle, continue burst next x x x l h h l h l l?h q read cycle, continue burst next x x x l h h l h h l?h tristate read cycle, continue burst next h x x l x h l h l l?h q read cycle, continue burst next h x x l x h l h h l?h tristate write cycle, continue burst next x x x l h h l l x l?h d write cycle, continue burst next h x x l x h l l x l?h d read cycle, suspend burst current x x x l h h h h l l?h q read cycle, suspend burst current x x x l h hhhhl?htristate read cycle, suspend burst current h x x l x h h h l l?h q read cycle, suspend burst current h x x l x hhhhl?htristate write cycle, suspend burst current x x x l h h h l x l?h d write cycle, suspend burst current h x x l x h h l x l?h d notes 1. x = do not care, h = logic high, l = logic low. 2. write = l when any one or more byte write enable signals, and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 3. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 4. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tristate. oe is a don't care for the remainder of the write cycle. 5. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cyc les. during a read cycle all d ata bits are tristate when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low).
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 11 of 34 truth table for read/write the truth table for read/write for cy7c1386d follows. [6, 7] function (cy7c1386d) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a ? (dq a and dqp a )hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c )hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d )hllhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b h l l l l h write all bytes hlllll write all bytes l x x x x x truth table for read/write the truth table for read/write for cy7c1387d follows. [6, 7] function (cy7c1387d) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write all bytes h l l l write all bytes l x x x notes 6. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 7. table only lists a partial listing of the byte write combinations. any combination of bw x is valid appropriate write is done based on which byte write is active.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 12 of 34 ieee 1149.1 serial boundary scan (jtag) the cy7c1387d incorporates a serial boundary scan test access port (tap). this part is fully compliant with 1149.1. the tap operates using jedec-standard 3.3 v or 2.5 v i/o logic levels. the cy7c1387d contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo can be left unconnected. upon power-up, the device comes up in a reset state which does not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. test data-out (tdo) the tdo output ball is used to serially clock data out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset in ternally to ensure that tdo comes up in a high z state. tap registers registers are connected betwe en the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 15 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload, and sa mple z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor specific 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in the identification register definitions on page 18 . tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in identification codes on page 18 . three of these instru ctions are listed as reserved and must not be used. the other five instructions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction after it is shifted in, the tap controller needs to be moved into the update-ir state.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 13 of 34 extest the extest instruction enables the preloaded data to be driven out through the system output pins . this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. idcode the idcode instruction causes a vendor specific 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. the sample z command places all sram outputs into a high z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. the user must be aware that t he tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. as there is a large difference in the clock frequenc ies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a de sign to stop (or slow) the clock during a sample/preload instructi on. if this is an issue, it is still possible to capture all othe r signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boun dary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required; that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest output bus tristate ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tristate mode. the boundary scan register has a special bit located at bit #85 (for 119-ball bga package) or bit #89 (for 165-ball fbga package). when this scan cell , called the ?extest output bus tristate,? is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high , it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latc hes into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is powered-up, and also when the tap controller is in the te st-logic-reset state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 14 of 34 tap controller state diagram the 0 or 1 next to each state represents the value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 15 of 34 tap controller block diagram tap timing diagram b ypa ss r egi s ter 0 i n s tru c tion r egi s ter 0 1 2 i denti c ation r egi s ter 0 1 2 2 9 30 3 1 . . . b oundary sc an r egi s ter 0 1 2 . . x . . . s ele c tion c ir c uitry t ck t ms t ap con t roller t di t do s ele c tion c ir c uitry t tl t e s t cl o ck (tck) 123456 t e s t m ode s e l e c t (tms) t th t e s t d ata -o ut (tdo) t cyc t e s t d ata -i n (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 16 of 34 tap ac switchi ng characteristics over the operating range parameter [8, 9] description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns notes 8. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 9. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 17 of 34 3.3 v tap ac test conditions input pulse levels ...............................................v ss to 3.3 v input rise and fall times ...................................................1 ns input timing reference levels .. ....................................... 1.5 v output reference levels ................................................ 1.5 v test load termination supply voltage ............................ 1.5 v 3.3 v tap ac out put load equivalent 2.5 v tap ac test conditions input pulse levels ............ .................................. .v ss to 2.5 v input rise and fall time ....................................................1 ns input timing reference levels ... .................................... 1.25 v output reference levels .............................................. 1.25 v test load termination supply vo ltage .......................... 1.25 v 2.5 v tap ac output load equivalent tdo 1 . 5v 20 p f z = 50 o 50 tdo 1 . 25v 20 p f z = 50 o 50 (0 c < t a < +70 c; v dd = 3.3 v 0.165 v unless otherwise noted) parameter [10] description test conditions min max unit v oh1 output high voltage i oh = ?4.0 ma, v ddq = 3.3 v 2.4 ? v i oh = ?1.0 ma, v ddq = 2.5 v 2.0 ? v v oh2 output high voltage i oh = ?100 a v ddq = 3.3 v 2.9 ? v v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 8.0 ma, v ddq = 3.3 v ? 0.4 v i ol = 8.0 ma, v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3 v ? 0.2 v v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 3.3 v 2.0 v dd + 0.3 v v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3 v ?0.5 0.7 v v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note 10. all voltages referenced to v ss (gnd).
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 18 of 34 identification regi ster definitions instruction field cy7c1387d (1 m 18) description revision number (31:29) 000 describes the version number device depth (28:24) [11] 01011 reserved for internal use. device width (23:18) 165-ball fbga 000110 de fines the memory type and architecture. cypress device id (17:12) 010101 defines the width and density. cypress jedec id code (11:1) 00000110100 al lows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. scan register sizes register name bit size ( 18) instruction 3 bypass 1 id 32 boundary scan order (165-ball fbga package) 89 identification codes instruction code description extest 000 captures i/o ring contents. places the bou ndary scan register between tdi and tdo. forces all sram outputs to high z state. idcode 001 loads the id regi ster with the vendor id code and plac es the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use. this instru ction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use. this instru ction is reserved for future use. reserved 110 do not use. this instru ction is reserved for future use. bypass 111 places the bypass register between td i and tdo. this operation does not affect sram operations. note 11. bit #24 is 1 in the register definitions fo r both 2.5 v and 3.3 v versions of this device.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 19 of 34 boundary scan order 165-ball bga [12, 13] bit # ball id bit # ball id bit # ball id 1 n6 31 d10 61 g1 2n7 32c11 62d2 3 n10 33 a11 63 e2 4p11 34b11 64f2 5p8 35a10 65g2 6r8 36b10 66h1 7r9 37a9 67h3 8p938b968j1 9 p10 39 c10 69 k1 10 r10 40 a8 70 l1 11 r11 41 b8 71 m1 12 h11 42 a7 72 j2 13 n11 43 b7 73 k2 14 m11 44 b6 74 l2 15 l11 45 a6 75 m2 16 k11 46 b5 76 n1 17 j11 47 a5 77 n2 18 m10 48 a4 78 p1 19 l10 49 b4 79 r1 20 k10 50 b3 80 r2 21 j10 51 a3 81 p3 22 h9 52 a2 82 r3 23 h10 53 b2 83 p2 24 g11 54 c2 84 r4 25 f11 55 b1 85 p4 26 e11 56 a1 86 n5 27 d11 57 c1 87 p6 28 g10 58 d1 88 r6 29 f10 59 e1 89 internal 30 e10 60 f1 notes 12. balls that are nc (no connect) are preset low. 13. bit#89 is preset high.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 20 of 34 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ..... ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .......?0.5 v to +4.6 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc voltage applied to outputs in tristate ...........................................?0.5 v to v ddq + 0.5 v dc input voltage .............. .............. ..... ?0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) .......................... > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / +10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 361 394 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch-up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculat ion. for more details refer to application note an54908 ?accelerated neutron ser testing and calculation of terrestrial failure rates?. electrical characteristics over the operating range parameter [14, 15] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [14] for 3.3 v i/o 2.0 v dd + 0.3 v v for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [14] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 a input current of mode input = v ss ?30 ? a input = v dd ? 5 a input current of zz input = v ss ?5 ? a input = v dd ? 30 a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 a notes 14. overshoot: v ih(ac) < v dd +1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 15. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 21 of 34 i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 5 ns cycle, 200 mhz ? 300 ma 6 ns cycle, 167 mhz ? 275 ma i sb1 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il f = f max = 1/t cyc 5 ns cycle, 200 mhz ? 150 ma 6 ns cycle, 167 mhz ? 140 ma i sb2 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = 0 all speeds ? 70 ma i sb3 automatic ce power-down current ? cmos inputs v dd = max, device deselected, or v in ? 0.3 v or v in > v ddq ? 0.3 v f = f max = 1/t cyc 5 ns cycle, 200 mhz ? 130 ma 6 ns cycle, 167 mhz ? 125 ma i sb4 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 all speeds ? 80 ma capacitance parameter [16] description test conditions 100-pin tqfp max 165-ball fbga max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 5 9 pf c clk clock input capacitance 5 9 pf c io i/o capacitance 5 9 pf electrical characteristics (continued) over the operating range parameter [14, 15] description test conditions min max unit thermal resistance parameter [16] description test conditions 100-pin tqfp package 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 28.66 20.7 c/w ? jc thermal resistance (junction to case) 4.08 4.0 c/w note 16. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 22 of 34 ac test loads and waveforms figure 3. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 23 of 34 switching characteristics over the operating range parameter [17, 18] description ?200 ?167 unit min max min max t power v dd (typical) to the first access [19] 1?1?ms clock t cyc clock cycle time 5.0 ? 6.0 ? ns t ch clock high 2.0 ? 2.2 ? ns t cl clock low 2.0 ? 2.2 ? ns output times t co data output valid after clk rise ? 3.0 ? 3.4 ns t doh data output hold after clk rise 1.3 ? 1.3 ? ns t clz clock to low z [20, 21, 22] 1.3?1.3?ns t chz clock to high z [20, 21, 22] ? 3.0 ? 3.4 ns t oev oe low to output valid ? 3.0 ? 3.4 ns t oelz oe low to output low z [20, 21, 22] 0?0?ns t oehz oe high to output high z [20, 21, 22] ? 3.0 ? 3.4 ns setup times t as address setup before clk rise 1.4 ? 1.5 ? ns t ads adsc , adsp setup before clk rise 1.4 ? 1.5 ? ns t advs adv setup before clk rise 1.4 ? 1.5 ? ns t wes gw , bwe , bw x setup before clk rise 1.4 ? 1.5 ? ns t ds data input setup before clk rise 1.4 ? 1.5 ? ns t ces chip enable setup before clk rise 1.4 ? 1.5 ? ns hold times t ah address hold after clk rise 0.4 ? 0.5 ? ns t adh adsp , adsc hold after clk rise 0.4 ? 0.5 ? ns t advh adv hold after clk rise 0.4 ? 0.5 ? ns t weh gw , bwe , bw x hold after clk rise 0.4 ? 0.5 ? ns t dh data input hold after clk rise 0.4 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.4 ? 0.5 ? ns notes 17. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 18. test conditions shown in (a) of figure 3 on page 22 unless otherwise noted. 19. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 20. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in (b) of figure 3 on page 22 . transition is measured 200 mv from steady-state voltage. 21. at any voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus cont ention condition, but reflect parameters gu aranteed over worst case user conditions . device is designed to achieve high z prior to low z under the same system conditions. 22. this parameter is sampled and not 100% tested.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 24 of 34 switching waveforms figure 4. read cycle timing [23] t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe,bw d ata o ut (dq) h ig h-z t doh t co adv t oehz t co s ing l e read burst read t oev t oelz t chz b ur s t w rap s around to it s initia l s tate t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a3) q(a2 + 3) a2 a3 d e s e l e c t c y cl e b ur s t c ontinued w it h ne w b a s e addre ss adv s u s pend s b ur s t dont care undefined x clz t note 23. full width write can be initiated by either gw low, or by gw high, bwe low, and bw x low.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 25 of 34 figure 5. write cycle timing [24] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x adv burst read burst write d(a2) d(a2 + 1) d(a3) d(a3 + 1) d(a2 + 3) a2 a3 e xtended burst write s ing l e write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes b yte w rite s igna ls are ignored f or ? r s t c y cl e wh en adsp initiate s b ur s t adsc extend s b ur s t adv s u s pend s b ur s t dont care undefined d(a1) h ig h-z d ata in (d) d ata o ut (q) note 24. full width write can be initiated by either gw low, or by gw high, bwe low, and bw x low.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 26 of 34 figure 6. read/write cycle timing [25, 26, 27] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces d ata o ut (q) h ig h-z adv s ing l e write d(a3) a4 a5 a6 d(a5) d(a6) d ata i n (d) burst read b a ck- to -b a ck reads h ig h-z q(a2) q(a1) q(a4) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co b a ck- to -b a ck writes a1 bwe, bw x a3 dont care undefined notes 25. full width write can be initiated by either gw low, or by gw high, bwe low, and bw x low. 26. the data bus (q) remains in high z following a write cycle, unless a new read access is initiated by adsp or adsc . 27. gw is high.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 27 of 34 figure 7. zz mode timing [28, 29] switching waveforms (continued) t zz i supply clk zz t zzrec all inputs ( ex c ept zz) dont care i ddzz t zzi t rzzi o utput s (q) h ig h-z deselect or read o n l y notes 28. device must be deselected when entering zz sleep mode. see cycl e descriptions table for all possible signal conditions to de select the device. 29. dqs are in high z when exiting zz sleep mode.
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 28 of 34 ordering information the table below contains only the parts that are currently avail able. if you do not see what you are looking for, please contac t your local sales representative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices. ordering code definitions speed (mhz) ordering code package diagram part and package type operating range 167 cy7c1386d-167axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial CY7C1387D-167AXC cy7c1387d-167bzi 51-85180 165-ball fbga (13 15 1.4 mm) industrial 200 cy7c1386d-200axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial temperature range: i = industrial; c = commercial; x = pb-free; x absent = leaded package type: bz = 165-pin fbga a = 100-pin tqfp speed grade: xxx = 167 mhz / 200 mhz process technology ? 90 nm 13xx = 1386 or 1387 1386 = dcd, 512 k 36 (18 mb) 1387 = dcd, 1 m 18 (18 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 13xx 7 - xxx x x d cy x c
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 29 of 34 package diagrams figure 10. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 figure 8. 165-ball fbga (13 15 1.4 mm) bb165d/ bw165d (0.5 ball diameter) package outline, 51-85180 51-85050 *d 51-85180 *e
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 30 of 34 acronyms document conventions units of measure acronym description bga ball grid array ce chip enable cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output jtag joint test action group lmbu logical multiple-bit upsets lsb least significant bit lsbu logical single-bit upsets msb most significant bit oe output enable sel single event latch-up sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius k ? kilohm mhz megahertz a microampere s microsecond ma milliampere mv millivolt mm millimeter ms millisecond ns nanosecond ? ohm % percent pf picofarad ps picosecond vvolt wwatt
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 31 of 34 document history page document title: cy7c1386d/cy7c1387d, 18-mbit (512 k 36/1 m 18) pipelined dcd sync sram document number: 38-05545 revision ecn orig. of change submission date description of change ** 254550 rkf see ecn new data sheet. *a 288531 syt see ecn updated features (removed 225 mhz speed bin information). updated selection guide (removed 225 mhz speed bin information). updated ieee 1149.1 serial boundary scan (jtag) (edited description for non-compliance with 1149.1). updated electrical characteristics (removed 225 mhz speed bin information). updated switching characteristics (removed 225 mhz speed bin information). updated ordering information (updated part numbers (added pb-free information for 100-pin tqfp, 119-ball bga and 165-ball fbga packages) and added comment of ?pb-free bg package s availability? below the ordering information). *b 326078 pci see ecn updated pin configurations (modified address expansion pins/balls in the pinouts for all packages as per jedec standards) updated ieee 1149.1 serial boundary scan (jtag) (updated tap instruction set (updated overview , updated extest , added extest output bus tristate )). updated identification register definitions (splitted device width (23:18) into two rows, one row for 119-ball bga and another row for 165-ball fbga and updated the values). updated electrical characteristics (updated test conditions for v oh and v ol parameters). updated thermal resistance (changed values of ? ja and ? jc parameters for 100-pin tqfp package from 31 and 6 ? c/w to 28.66 and 4.08 ? c/w respectively, changed values of ? ja and ? jc parameters for 119-ball bga package from 45 and 7 ? c/w to 23.8 and 6.2 ? c/w respectively, changed values of ? ja and ? jc parameters for 165-ball fbga package from 46 and 3 ? c/w to 20.7 and 4.0 ? c/w respectively). updated ordering information (updated part numbers and removed comment of ?pb-free bg packages availabilit y? below the ordering information). *c 418125 nxr see ecn changed status from preliminary to final. changed address of cypress semicondu ctor corporation on page# 1 from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (changed the description of i x parameter from input load current to input leakage current, changed minimum and maximum values of i x parameter for input cu rrent of mode from ?5 ? a and 30 ? a to ?30 ? a and 5 ? a, changed minimum and maximum values of i x parameter for input current of zz from ?30 ? a and 5 ? a to ?5 ? a and 30 ? a, updated note 15 (changed v ih < v dd to v ih < v dd )). updated ordering information (updated part numbers and replaced package name column with package diagram in the ordering information table). *d 475009 vkn see ecn updated tap ac switching characteristics (changed minimum values of t th and t tl parameters from 25 ns to 20 ns, changed maximum value of t tdov parameter from 5 ns to 10 ns). updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers).
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 32 of 34 *e 793579 vkn see ecn added part numbers cy7c1386f and cy7c1387f updated features (included all information related to cy7c1386f and cy7c1387f). updated functional description (included all information related to cy7c1386f and cy7c1387f). updated logic block diagram and added a note regarding chip enable ?cy7c1386f and cy7c1387f have only 1 chip enable (ce 1 ).?. updated pin configurations (included all information related to cy7c1386f and cy7c1387f). updated functional overview (included all information related to cy7c1386f and cy7c1387f). updated truth table (included all information related to cy7c1386f and cy7c1387f). updated truth table for read/write (included all information related to cy7c1386f and cy7c1387f). updated truth table for read/write (included all information related to cy7c1386f and cy7c1387f). updated ieee 1149.1 serial boundary scan (jtag) (included all information related to cy7c1386f and cy7c1387f). updated identification register definitions (included all information related to cy7c1386f and cy7c1387f). updated ordering information (updated part numbers). *f 2756940 vkn 08/27/2009 added neutron soft error immunity . modified ordering information (by including parts that are available) and modified the disclaimer for the ordering information . *g 3006369 njy 08/12/10 added ordering code definitions . added acronyms . updated in new template. *h 3309506 osn 07/12/2011 updated package diagrams . added units of measure . updated in new template. document history page (continued) document title: cy7c1386d/cy7c1387d, 18-mbit (512 k 36/1 m 18) pipelined dcd sync sram document number: 38-05545 revision ecn orig. of change submission date description of change
cy7c1386d cy7c1387d document number: 38-05545 rev. *j page 33 of 34 *i 3541411 prit 03/03/2012 updated features (removed all information related to cy7c1386f and cy7c1387f). updated functional description (removed all information related to cy7c1386f and cy7c1387f, removed the notes ?for best practices or recommendations, please refer to the cypress application note an1064, sram system design guidelines on www.cypress.com .? and ?ce 3 and ce 2 are for 100-pin tqfp and 165-ball fbga packages only. 119-ball bga is offered only in single chip enable.?). updated selection guide (removed 250 mhz speed bin information). updated logic block diagram ? cy7c1386d (removed all information related to cy7c1386f and cy7c1387f). updated logic block diagram ? cy7c1387d (removed all information related to cy7c1386f and cy7c1387f). updated pin configurations (removed all information related to cy7c1386f and cy7c1387f). updated pin definitions (removed the note ?ce 3 and ce 2 are for 100-pin tqfp and 165-ball fbga packages only. 1 19-ball bga is offered only in single chip enable.? and its references in the same section). updated functional overview (removed all information related to cy7c1386f and cy7c1387f, removed the note ?ce 3 and ce 2 are for 100-pin tqfp and 165-ball fbga packages only. 119-ball bga is offered only in single chip enable.? and its references in the same section). updated truth table (removed all information related to cy7c1386f and cy7c1387f). updated truth table for read/write (removed all information related to cy7c1386f and cy7c1387f). updated truth table for read/write (removed all information related to cy7c1386f and cy7c1387f). updated ieee 1149.1 serial boundary scan (jtag) (removed all information related to cy7c1386f and cy7c1387f). updated identification register definitions (removed all information related to cy7c1386f and cy7c1387f). updated scan register sizes (removed bit size ( 36) information). updated boundary scan order (removed all 119-ball bga information). updated electrical characteristics (removed 250 mhz speed bin information). updated capacitance (removed all 119-ball bga information). updated thermal resistance (removed all 119-ball bga information). updated switching characteristics (removed 250 mhz speed bin information). updated ordering information (updated part numbers) and updated ordering code definitions . updated package diagrams . *j 3690005 prit 07/24/2012 no technical ch anges. completing sunset review. document history page (continued) document title: cy7c1386d/cy7c1387d, 18-mbit (512 k 36/1 m 18) pipelined dcd sync sram document number: 38-05545 revision ecn orig. of change submission date description of change
document number: 38-05545 rev. *j revised july 24, 2012 page 34 of 34 intel and pentium are registered trademarks, and i486 is a trademark of intel corporation. powerpc is a trademark of ibm corpor ation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1386d cy7c1387d ? cypress semiconductor corporation, 2004-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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